1. Field of the Invention
The invention generally relates to southbridges and corresponding integrated circuit chips, computer systems and methods, and in particular to the implementation of ordering rules when transmitting commands of different types.
2. Description of the Related Art
Integrated circuit chips are often used for data processing and are known to comprise a number of different circuit units. Generally, each circuit unit is for performing a specific function and of course, there may be different circuit units provided on one chip for performing the same function, or performing different functions. The circuit units may operate sequentially in time or simultaneously, and they may function independently from each other, or dependent on the operation of other circuit units.
In the latter case, the circuit units are usually interconnected via an interface to allow the circuit units to interchange data needed for making the operation of one circuit unit dependent on the operation of the other circuit unit. The data exchange is often done by sending transactions from one circuit unit to the other circuit unit. A transaction is a sequence of packets that are exchanged between the circuit units and that result in a transfer of information. The circuit unit initiating a transaction is called the source (or master), and the circuit unit that ultimately services the transaction on behalf of the source is called target. It is to be noted that there may also be intermediary units between the source and the target.
Transactions may be used to place a request, or to respond to a received request. Taking the requests, there may be distinguished posted request from non-posted requests, dependent on whether the request requires a response. Specifically, a non-posted request is a request that requires a response while a posted request does not require a response.
When focusing on the functions which are performed by the interconnected circuit units, the circuit units can often be divided into hosts and devices. The term host then means a circuit unit that provides services to the dependent device. A transaction from the host to the device is said to be downstream while a transaction in the other direction is said to be upstream. In bi-directional configurations, both the host and the device may send and receive requests and responses so that a device may be source as well as target, and also the host may function as source or target.
A field where such integrated circuit chips are widely used are personal computers. Referring to FIG. 1, the hardware components of a common motherboard layout are depicted. It is to be noted that this figures shows only one example of a motherboard layout, and other configurations exist as well. The basic elements found on the motherboard of FIG. 1 may include the CPU (Central Processing Unit) 100, a northbridge 105, a southbridge 110, and system memory 115.
The northbridge 105 is usually a single chip in a core-logic chipset that connects the processor 100 to the system memory 115 and, e.g., to the AGP (Accelerated Graphic Port) and PCI (Peripheral Component Interface) buses. The PCI bus is commonly used in personal computers for providing a data path between the processor 100 and peripheral devices like video cards, sound cards, network interface cards and modems. The AGP bus is a high-speed graphic expansion bus that directly connects the display adapter and system memory 115. AGP operates independently of the PCI bus. It is to be noted that other motherboard layouts exist that have no northbridge in it, or that have a northbridge without AGP or PCI options.
The southbridge 110 is usually the chip in a system core-logic chipset that controls the IDE (Integrated Drive Electronics) or EIDE (Enhanced IDE) bus, controls a USB (Universal Serial Bus) bus that provides plug-and-play support, controls a PCI-ISA (Industry Standard Architecture) bridge, manages the keyboard/mouse controller, provides power management features, and controls other peripherals.
Thus, common personal computers include southbridges 110 which are integrated circuit chips substantially as described above. Conventionally, the southbridge 110 and the northbridge 105 are interconnected by the PCI bus acting as system bus so that the northbridge 105 works as host-to-PCI bridge forming a link between the host bus that connects to the processor 100, and the PCI bus whereas the southbridge 110 works as, e.g., PCI-to-ISA bus where the ISA (Industry Standard Architecture) bus is the I/O bus. However, other chipset arrangements exist in which the northbridge 105 operates as memory controller hub and the southbridge 110 as I/O controller hub. In such structures, the northbridge 105 and the southbridge 110 are no longer interconnected by a system bus but by a specific hub interface.
To satisfy the demands for high-speed chip-to-chip communication in such hub interfaces, the HyperTransport™ technology was developed which provides a high-speed, high-performance point-to-point on-board link for interconnecting integrated circuits on a motherboard. It can be significantly faster than a PCI bus for an equivalent number of pins. The HyperTransport technology is designed to provide significantly more bandwidth than current technologies, to use low-latency responses, to provide low pin count, to be compatible with legacy computer buses, to be extensible to new system network architecture buses, to be transparent to operating systems, and to offer little impact on peripheral drivers.
The hardware components of a HyperTransport compliant southbridge device (or I/O hub) is depicted in FIG. 2. A number of bus masters 230–260 are provided for controlling peripheral system components. The controllers may for instance include a hard disk controller 230, an ethernet controller 240, a USB (Universal Serial Bus) controller 250, and an AC (Audio Codec) '97 controller 260. These controllers act as bus masters to interact with a transmit engine 220 and a receive engine 210 of the device. The transmit engine 220 receives requests from the controllers 230–260 and performs an arbitration to select at any one time one of the requestors 230–260. Based on the received requests, the transmit engine 220 sends commands to the HyperTransport interface unit 200 that interfaces to a HyperTransport compliant link. Received responses are supplied from the HyperTransport interface unit 200 to the receive engine 210 where the responses are forwarded to the respective controllers 230–260 that were the originators of the requests. Thus, the HyperTransport interface is a split transaction interface, i.e., requests and responses are transferred on the bus as completely decoupled and independent transactions.
The HyperTransport specification defines three types of command packets: posted commands, non-posted commands, and responses. Ordering rules are defined for all types of I/O traffic. Ordered operations that return responses (reads or non-posted writes) are required to complete at the target in the correct order, and all I/O devices must be able to accept responses out of order or restrict themselves to one outstanding non-posted request. A bridge that is between a HyperTransport technology device and an I/O protocol that requires responses to be returned in order must provide sufficient buffering to be able to reorder as many responses as it may have outstanding requests.
As mentioned above, the HyperTransport technology recognizes three types of traffic: posted requests, non-posted requests, and responses, each in a separate virtual channel. These three types of traffic can be distinguished by their command encoding. Requests and responses both have a May Pass Posted Writes (PassPW) bit. The packet ordering rules can then be summarized by:
Row PassNon-postedColumn?Posted RequestRequestResponsePostedPassPW: Yes/NoYesYesrequest!PassPW: NoNon-postedPassPW: Yes/NoYes/NoYes/NoRequest!PassPW: NoResponsePassPW: Yes/NoYesYes/No!PassPW: No
In the table, “No” indicates the subsequently issued transaction is not allowed to complete before the previous transaction. “Yes” indicates the subsequently issued transaction must be able to pass the previous transaction, and the packet type given in the column cannot be permitted to block the packet type given in the row at any point in the HyperTransport fabric or host. “Yes/No” indicates the subsequently issued transaction may optionally be allowed to complete before the previous transaction if there is any advantage to doing so. In this case, there are no ordering requirements between the two transactions. However, support for reordering is not required and failure to reorder the packets will not lead to deadlock.
Since therefore, different command types have to fulfil different rules, the most common way to implement the HyperTransport technology ordering rules is to provide multiple buffers which are each dedicated to one of the command types. This makes it easy to obtain the next command to be transmitted simply by selecting the respective buffer and reading out the first command in that buffer. However, this approach has some disadvantages.
One problem with this prior art scheme is that each time a command is received, its command type needs to be determined. Thus, a type detection is to be performed at the time of buffering the command, in order to determine the buffer to which the command is to be written. This is rather inefficient and reduces the overall operation speed.
A further problem with separate buffers is that the buffers require a significant amount of total buffer space to be sure that the buffers do not run empty. Thus, conventional circuits used to fulfil the command ordering rules are large in size and lead to high circuit development and manufacturing costs. Moreover, the prior art approaches are disadvantageous since they reduce the design robustness what makes it difficult to verify the design.
Besides the HyperTransport technology, other interface techniques exist where commands of different types are transmitted in a manner so as to fulfil certain ordering rules. These interface techniques have the same or similar problems as described above with respect to the HyperTransport technology.